This application relies for priority upon Korean Patent Application No. 2001-005975, filed on Feb. 7, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention generally relates to the field of semiconductor devices. More particularly, the invention is directed to a method of forming a semiconductor device having high-density contacts.
2. Description of the Related Art
To manufacture high-density semiconductor devices, multi-layer interconnections have been utilized and the formation density of contacts has been increased. Thus, it is necessary to further scale down the devices and to reduce the width of contact plugs and contact-to-contact spacing from their old levels. Contact resistance, however, can increase while reducing the contact plug width. Also, contact-to-contact isolation can be difficult to achieve while reducing the contact-to-contact spacing.
With the resolution of the current exposing apparatus, the semiconductor industry has encountered many problems in contact formation especially due to a reduction in the contact width and the spacing between contacts. For example, adjacent patterns can be attached to each other because of light diffraction. As the width of a contact decreases, the area of photoresist exposed to light is also reduced. Further, some portions of the exposed photoresist are not entirely photosensed and thus undesirably partially remain even after development. It is widely known that it is difficult to form a contact having a spacing of 0.15 xcexcm, considering the resolution limit and light wavelength of a current exposing apparatus such as a stepper.
On the other hand, since light can be irradiated horizontally or vertically for forming an interconnection line pattern, even the area under photoresist can be photosensed. Accordingly, interconnection lines can be even smaller than the minimum width of the contact.
However, despite these difficulties in forming a contact having a spacing of 0.15 xcexcm, there have been ever increasing demands for semiconductor products having a contact width of 0.15 xcexcm or less. In order to meet these demands, exposing apparatuses of higher resolution have been developed and technologies for reducing light wavelength have been suggested. In addition, there have been various approaches to form a very fine pattern.
One prior art approach uses thermal flow characteristics of a photoresist. In that approach, the smallest-possible photoresist pattern is initially formed to ultimately reduce the width of contact patterns. Thus, a photoresist pattern having the minimum width under the current technologies is formed. The width of the pattern is increased by heating the photoresist while the width between photoresist patterns decreases. That is, a window for a contact is formed with a wide width xe2x80x9cAxe2x80x9d, as shown in FIG. 1. A photoresist pattern having a window is extended inwardly to reduce a window width to xe2x80x9cCxe2x80x9d, as shown in FIG. 2. If the underlying layer is etched to form a contact using a photoresist as a mask, the size or width of a contact hole can be decreased.
This photoresist thermal flow technique is effective in the reduction of the pattern width up to a critical value or less by the normal exposure, while it is not effective to narrow the spacing between adjacent contact patterns, as can be seen in FIG. 2. If the spacing is reduced up to xe2x80x9cC,xe2x80x9d i.e., a minimum distance (F), adjacent windows for a contact can be undesirably connected or attached to each other.
In this regard, a mask pattern is designed so that adjacent contact holes are not connected to each other by setting the minimum distance using prior experience. If the pattern-to-pattern spacing is reduced to be less than the minimum distance length, one group of adjacent contacts is formed first and the other group is formed later. However, the increase in the number of the pattern exposure also increases manufacturing costs. Worse yet, an error of alignment between pattern masks can be accumulated and this can aggravate processing defects.
FIGS. 4-7 illustrate an example of processing defects resulting from the accumulation of the alignment error between pattern masks, with a top plan view xe2x80x9cAxe2x80x9d and its cross-sectional view xe2x80x9cB.xe2x80x9d
Referring to FIGS. 4A-4B, a first interlayer insulating layer 30 and an auxiliary layer 13 are sequentially stacked on a substrate 10 in which a conductive region 20 is formed. A pre-first photoresist pattern having a width xe2x80x9cAxe2x80x9d is formed, and is changed to a first photoresist pattern 11 in which a window of width xe2x80x9cCxe2x80x9d is formed through a thermal flow technique. Using the first photoresist pattern 11 as a mask, the auxiliary layer 13 is etched to form a first window 15 of width xe2x80x9cCxe2x80x9d thereon. In this case, the auxiliary layer 13 acts as a hard mask. An initial distance xe2x80x9cBxe2x80x9d becomes xe2x80x9cBxe2x80x2xe2x80x9d that is the distance between first windows represented by a solid line in the first photoresist pattern 11 after the thermal flow. Then, the first photoresist pattern 11 is removed.
Referring to FIGS. 5A-5B, a pre-second photoresist pattern is formed on the auxiliary layer 13. In the pre-second photoresist pattern, two windows of width xe2x80x9cAxe2x80x9d are formed so that the distance from the first window can be less than the minimum distance (F). Through the thermal flow, the pre-second photoresist pattern is changed to a second photoresist pattern 19 in which two second windows of width xe2x80x9cCxe2x80x9d are formed. Using the second photoresist pattern 19 as a mask, the auxiliary layer 13 is etched to form a second window 17 of width xe2x80x9cCxe2x80x9d in the auxiliary layer 13. The second photoresist pattern is then etched by conventional techniques such as ashing and stripping.
Based upon an original design to the first window 15, the second window 17 maintains the width xe2x80x9cCxe2x80x9d that is less than the minimum distance (F). Because of an alignment error, the second window 17 practically moves left by limit of error in the drawings. As a result, the distance between the first and second windows is reduced to xe2x80x9cCxe2x88x92H(=C/2)xe2x80x9d.
Referring to FIGS. 6A-6B, using the auxiliary layer 13 with the first and second windows 15 and 17 as a mask, a first interlayer insulating layer 30 is etched to expose a conductive region 20 of the substrate 10. A conductive layer is formed on the resulting structure and is subsequently planarized until the surface of the auxiliary layer 13 is exposed, thereby forming first and second conductive plugs 21 and 23 at first and second window areas, respectively.
Referring to FIGS. 7A-7B, a second interlayer insulating layer 40 is formed on the substrate 10 in which the first and second plugs 21 and 23 are formed. The second interlayer insulating layer 40 is patterned to form a groove therein. An interconnection layer is formed thereon, and an interconnection is formed in the second interlayer insulating layer 40 by planarizing techniques such as chemical mechanical polishing (CMP). The distance between first and second interconnection pattern 45 and 44 is identical to the distance between the first and second windows 15 and 17, i.e., the distance xe2x80x9cC ( less than F)xe2x80x9d. The width of the interconnection patterns 45 and 44 is xe2x80x9cD(xe2x89xa7C)xe2x80x9d.
During this process, the groove is misaligned to move away from a dotted line position (original position) to a solid line position (moved position) along the direction an arrow by xe2x80x9cHxe2x80x9d. As a result, the second contact plug 23 connected to the second interconnection pattern 44 can be undesirably connected to the fist interconnection pattern 45. This results in a fatal semiconductor device failure. Also, an overlap area of the second contact plug 23 and the second interconnection pattern 44 is too small to form the proper interconnection therebetween.
Accordingly, there is a need to address this and other limitations in the prior art.
The present invention provides methods for forming semiconductor integrated circuit devices. According to one embodiment, an interlayer insulating layer and an auxiliary layer having interconnection line patterns are sequentially formed on a substrate in which a conductive region is formed. Next, a contact photoresist pattern having bar-shaped patterns is formed on the auxiliary layer. The bar-shaped patterns extend across or are substantially orthogonal to the interconnection line pattern formed in the auxiliary layer. Then, the interlayer insulating layer is etched at a contact region using the contact photoresist pattern and the auxiliary layer as an etching mask. Subsequently, the interlayer insulating layer is etched using the auxiliary layer as an etching mask to form a contact hole that extends through the interlayer insulating layer to the conductive region and to form an interconnection groove in an upper portion of the interlayer insulating layer. The contact hole and the interconnection groove are filled with a conductive layer to form contacts and interconnection lines.
According to another embodiment of the present invention, after removing the auxiliary layer, a conductive layer is stacked thereon and is planarized until a surface of the interlayer insulating layer is exposed. Alternatively, the conductive layer is stacked on the auxiliary layer without removing the auxiliary layer. Thereafter, the conductive layer and the auxiliary layer are planarized down to a surface of the interlayer insulating layer. Thus, a contact and an interconnection are formed.
A mask for interconnection and a bar-shaped mask for contact are used to perform exposure in twice. Thus, problems resulting from alignment of exposure three times can be reduced. With the present invention, because the pitch or distance between adjacent patterns becomes definite, x-axis spacing and y-axis spacing between contacts are not changed during exposure.